13 commits

Author	SHA1	Message	Date
dundargoc	4612212c72	docs: fix typos	2023-02-23 11:39:43 -08:00
ObserverOfTime	ee0834d59b	highlights(verilog): fix captures	2022-11-26 13:17:51 +02:00
Lewis Russell	37398c7d68	feat(spell): support more languages	2022-09-26 13:47:12 +01:00
Jade Lovelace	c2d2557526	verilog highlight: add some keywords, tidy keywords (#2432) ... * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`	2022-02-02 08:13:01 +01:00
Sergio Alejandro Vargas	820b4a9c21	Use @keyword.function consistently	2021-07-06 00:53:40 +02:00
antonk52	90f15d9bf7	feat(keywords) merge return and yield into keyword.return group	2021-07-04 21:49:17 +02:00
antonk52	bd9095e969	feat(keywords) add keyword.return & keyword.yield	2021-07-04 21:49:17 +02:00
Stephan Seitz	acbb453f57	Update verilog to 0.19.2	2021-03-16 18:52:43 +01:00
zegervdv	6731bcbf7b	Add locals for verilog	2020-11-21 14:43:08 +01:00
zegervdv	6cc1c28f68	Add missing verilog keywords	2020-11-21 14:43:08 +01:00
zegervdv	d59b4810a6	Improve highlighting of port declarations in verilog	2020-11-21 14:43:08 +01:00
zegervdv	7fa67b490f	Improve highlighting for generate blocks	2020-11-16 18:43:00 +01:00
Zeger Van de Vannet	392c4b978b	Add verilog/systemverilog queries	2020-10-20 16:33:13 +02:00