Add locals for verilog

queries/verilog/highlights.scm

@@ -19,8 +19,20 @@
   "interface"
   "endinterface"
   "modport"
+  "package"
+  "endpackage"
+  "fork"
+  "join"
+  "join_none"
+  "join_any"
+  "assert"
 ] @keyword
 
+[
+  "begin"
+  "end"
+] @label
+
 [
   (always_keyword)
   "generate"
@@ -28,6 +40,7 @@
   "foreach"
   "repeat"
   "forever"
+  "initial"
   "while"
 ] @repeat
 
@@ -38,15 +51,6 @@
   "endcase"
 ] @conditional
 
-[
-  "begin"
-  "end"
-  "fork"
-  "join"
-  "join_none"
-  "join_any"
-] @label
-
 (comment) @comment
 
 (include_compiler_directive) @constant.macro
@@ -65,9 +69,12 @@
  (package_identifier
   (simple_identifier) @constant))
 
-(module_ansi_header
- (parameter_port_list
-  "#" @constructor))
+(package_declaration
+ (package_identifier
+  (simple_identifier) @constant))
+
+(parameter_port_list
+ "#" @constructor)
 
 [
   "="
@@ -140,7 +147,10 @@
 (net_port_type1
  (simple_identifier) @type)
 
-(double_quoted_string) @string
+[
+  (double_quoted_string)
+  (string_literal)
+] @string
 
 [
   (include_compiler_directive)
@@ -228,6 +238,14 @@
 
 (struct_union) @type
 
+[
+  "enum"
+] @type
+
+(enum_name_declaration
+ (enum_identifier
+  (simple_identifier) @constant))
+
 (type_declaration
  (simple_identifier) @type)