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nvim-treesitter/runtime/queries/systemverilog/highlights.scm

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Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
; Keywords
[
fix(highlights): improve consistency
2024-01-09 11:50:31 +02:00
"begin"
"end"
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
"generate"
"endgenerate"
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
(module_keyword)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
"endmodule"
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
"program"
"endprogram"
Add locals for verilog
2020-11-18 21:38:58 +01:00
"package"
"endpackage"
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
"checker"
"endchecker"
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
"config"
"endconfig"
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
"pure"
"virtual"
"extends"
"implements"
"super"
(class_item_qualifier)
"parameter"
"localparam"
"defparam"
"assign"
"modport"
Add locals for verilog
2020-11-18 21:38:58 +01:00
"fork"
"join"
"join_none"
"join_any"
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
"default"
"break"
"tagged"
"extern"
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
"alias"
"posedge"
"negedge"
"bind"
"expect"
"type"
"void"
"coverpoint"
"cross"
"nettype"
"export"
"force"
"release"
"timeunit"
"timeprecision"
"sequence"
"endsequence"
"property"
"endproperty"
"clocking"
"endclocking"
"covergroup"
"endgroup"
"specify"
"endspecify"
"primitive"
"endprimitive"
"wait"
"wait_order"
"const"
"constraint"
"unique"
"do"
"genvar"
"inside"
"rand"
"continue"
"randc"
"event"
"global"
"ref"
"initial"
fix(verilog): update queries (#7400) 1. Add "string" as a keyword 2. Fix issue where non-type.builtin fields are captured when using (data_type) as type.builtin 3. Add generate label
2024-11-24 17:44:23 +08:00
"string"
highlights(verilog): fix captures
2022-10-28 17:08:00 +03:00
(unique_priority)
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(bins_keyword)
(always_keyword)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
] @keyword
feat: more `@keyword.type` captures
2024-04-23 12:23:15 -07:00
[
"class"
"endclass"
"interface"
"endinterface"
"enum"
"struct"
"union"
fix(verilog): various touch-ups
2024-06-17 18:19:08 -07:00
"typedef"
feat: more `@keyword.type` captures
2024-04-23 12:23:15 -07:00
] @keyword.type
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
[
"function"
"endfunction"
"task"
"endtask"
] @keyword.function
feat(keywords) merge return and yield into keyword.return group
2021-07-04 20:24:25 +03:00
"return" @keyword.return
feat(keywords) add keyword.return & keyword.yield
2021-07-04 19:55:59 +03:00
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
[
"for"
"foreach"
"repeat"
"forever"
"while"
feat!: align standard captures with upstream Problem: Sharing highlight queries with upstream tree-sitter and Helix is difficult. Solution: Where reasonable, use capture names in tree-sitter's standard list or Helix's Atom-style hierarchy. Specifically: * tree-sitter "standard capture names" (https://github.com/tree-sitter/tree-sitter/blob/3f44b896852eb7daaa6df4fb778c9bb52c70c815/highlight/src/lib.rs#L20-L72): - `@parameter` -> `@variable.parameter` - `@field` -> `@variable.member` - `@namespace` -> `@module` - `@float` -> `@number.float` - `@symbol` -> `@string.special.symbol` - `@string.regex` -> `@string.regexp` - `@text.*` -> `@markup.*` (`strong`, `italic`, `link`, `strikethrough`; with exceptions; see below) - `@text.title` -> `@markup.heading` - `@text.literal` -> `@markup.raw` - `@text.reference` -> `@markup.link` - `@text.uri` -> `@markup.link.url` (in markup links) - `@string.special` -> `@markup.link.label` (non-url links) - `@punctuation.special` -> `@markup.list` (markdown lists only; move subitems from `@text.todo`) * Helix captures (https://docs.helix-editor.com/master/themes.html#syntax-highlighting): - `@method` -> `@function.method` - `@method.call` -> `@function.method.call` - `@text.{todo,warning,note,danger}` -> `@comment.{error,warning,hint,info,todo}` - `@text.diff.{add,delete,}` -> `@diff.{plus,minus,delta}` - `@text.uri` -> `@string.special.url` (outside markup) - `@preproc` -> `@keyword.directive` - `@define` -> `@keyword.directive`(`.define`?) - `@storageclass` -> `@keyword.storage` - `@conditional` -> `@keyword.conditional` - `@debug` -> `@keyword.debug` - `@exception` -> `@keyword.exception` - `@include` -> `@keyword.import` - `@repeat` -> `@keyword.repeat` * cleanup - remove some redundant `@conceal` (but still allow it for conceal-only patterns) - remove obsolete `@error` (syntax linting is out of scope for this repo) - sort, cleanup capture list in `CONTRIBUTING.md`
2023-12-24 10:00:20 +01:00
] @keyword.repeat
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; for
(loop_generate_construct
(generate_block
[
"begin"
"end"
] @keyword.conditional))
; foreach
(loop_statement
(statement
(statement_item
(seq_block
[
"begin"
"end"
] @keyword.conditional))))
; repeat forever while
(loop_statement
(statement_or_null
(statement
(statement_item
(seq_block
[
"begin"
"end"
] @keyword.conditional)))))
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
[
"if"
"else"
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
"iff"
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
(case_keyword)
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
"endcase"
feat!: align standard captures with upstream Problem: Sharing highlight queries with upstream tree-sitter and Helix is difficult. Solution: Where reasonable, use capture names in tree-sitter's standard list or Helix's Atom-style hierarchy. Specifically: * tree-sitter "standard capture names" (https://github.com/tree-sitter/tree-sitter/blob/3f44b896852eb7daaa6df4fb778c9bb52c70c815/highlight/src/lib.rs#L20-L72): - `@parameter` -> `@variable.parameter` - `@field` -> `@variable.member` - `@namespace` -> `@module` - `@float` -> `@number.float` - `@symbol` -> `@string.special.symbol` - `@string.regex` -> `@string.regexp` - `@text.*` -> `@markup.*` (`strong`, `italic`, `link`, `strikethrough`; with exceptions; see below) - `@text.title` -> `@markup.heading` - `@text.literal` -> `@markup.raw` - `@text.reference` -> `@markup.link` - `@text.uri` -> `@markup.link.url` (in markup links) - `@string.special` -> `@markup.link.label` (non-url links) - `@punctuation.special` -> `@markup.list` (markdown lists only; move subitems from `@text.todo`) * Helix captures (https://docs.helix-editor.com/master/themes.html#syntax-highlighting): - `@method` -> `@function.method` - `@method.call` -> `@function.method.call` - `@text.{todo,warning,note,danger}` -> `@comment.{error,warning,hint,info,todo}` - `@text.diff.{add,delete,}` -> `@diff.{plus,minus,delta}` - `@text.uri` -> `@string.special.url` (outside markup) - `@preproc` -> `@keyword.directive` - `@define` -> `@keyword.directive`(`.define`?) - `@storageclass` -> `@keyword.storage` - `@conditional` -> `@keyword.conditional` - `@debug` -> `@keyword.debug` - `@exception` -> `@keyword.exception` - `@include` -> `@keyword.import` - `@repeat` -> `@keyword.repeat` * cleanup - remove some redundant `@conceal` (but still allow it for conceal-only patterns) - remove obsolete `@error` (syntax linting is out of scope for this repo) - sort, cleanup capture list in `CONTRIBUTING.md`
2023-12-24 10:00:20 +01:00
] @keyword.conditional
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
[
"="
"-"
"+"
"/"
"*"
"^"
"&"
"|"
"&&"
"||"
"<="
"=="
"!="
"==="
"!=="
"-:"
"<"
">"
">="
"%"
">>"
"<<"
"|="
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
"|=>"
"|->"
">>>"
"<<<"
"->>"
"->"
"=>"
"*>"
".*"
highlights(verilog): fix captures
2022-10-28 17:08:00 +03:00
(unary_operator)
Improve highlighting for generate blocks
2020-11-16 18:32:51 +01:00
(inc_or_dec_operator)
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(queue_dimension)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
] @operator
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
"#" @constructor
[
";"
"::"
","
"."
":"
] @punctuation.delimiter
(conditional_expression
[
"?"
":"
] @keyword.conditional.ternary)
[
"["
"]"
"("
")"
"{"
"}"
"'{"
] @punctuation.bracket
fix(verilog): various touch-ups
2024-06-17 18:19:08 -07:00
highlights(verilog): fix captures
2022-10-28 17:08:00 +03:00
[
"or"
"and"
] @keyword.operator
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
[
"input"
"output"
"inout"
"signed"
"unsigned"
"assert"
"cover"
"assume"
"disable"
"automatic"
"static"
(dpi_function_import_property)
(dpi_task_import_property)
] @keyword.modifier
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
[
"include"
"import"
feat(systemverilog)!: update parser and queries Breaking changes: 1. `(comment)` node split into `(one_line_comment)` and `(block_comment)` 2. named `(directive_foo)` nodes replaced by anonymous `"'foo"` (with backtick!) nodes -- but not consistently
2025-08-01 18:15:49 +02:00
"`include"
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
] @keyword.import
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(systemverilog)!: update parser and queries Breaking changes: 1. `(comment)` node split into `(one_line_comment)` and `(block_comment)` 2. named `(directive_foo)` nodes replaced by anonymous `"'foo"` (with backtick!) nodes -- but not consistently
2025-08-01 18:15:49 +02:00
[
(one_line_comment)
(block_comment)
] @comment @spell
chore: query formatting
2024-01-06 15:05:50 +09:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
[
"@"
(cycle_delay_range)
(delay_control)
(cycle_delay)
(attribute_instance)
] @attribute
(attribute_instance
(attr_spec
(simple_identifier) @property))
[
(integral_number)
(unbased_unsized_literal)
(fixed_point_number)
(unsigned_number)
] @number
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
[
(net_type)
fix(verilog): update queries (#7400) 1. Add "string" as a keyword 2. Fix issue where non-type.builtin fields are captured when using (data_type) as type.builtin 3. Add generate label
2024-11-24 17:44:23 +08:00
(integer_vector_type)
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(time_unit)
fix(verilog): update queries (#7400) 1. Add "string" as a keyword 2. Fix issue where non-type.builtin fields are captured when using (data_type) as type.builtin 3. Add generate label
2024-11-24 17:44:23 +08:00
(integer_atom_type)
fix(verilog): capture `(non_integer_type)` as `@type.builtin`
2025-01-25 15:52:24 +07:00
(non_integer_type)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
] @type.builtin
fix(verilog): update queries (#7400) 1. Add "string" as a keyword 2. Fix issue where non-type.builtin fields are captured when using (data_type) as type.builtin 3. Add generate label
2024-11-24 17:44:23 +08:00
(data_type
(simple_identifier) @type.builtin)
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; variable
(list_of_variable_decl_assignments
(variable_decl_assignment
name: (simple_identifier) @variable))
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(hierarchical_identifier
(simple_identifier) @variable)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(tf_port_item
(simple_identifier) @variable)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
port_name: (simple_identifier) @variable
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(port
(simple_identifier) @variable)
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(list_of_port_identifiers
(simple_identifier) @variable)
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(net_lvalue
(simple_identifier) @variable)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(sequence_port_item
(simple_identifier) @variable)
highlights(verilog): fix captures
2022-10-28 17:08:00 +03:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(property_port_item
(simple_identifier) @variable)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(net_decl_assignment
(simple_identifier) @variable)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; variable.member
(hierarchical_identifier
(simple_identifier)
(simple_identifier) @variable.member)
fix(verilog): various touch-ups
2024-06-17 18:19:08 -07:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(select
(simple_identifier) @variable.member)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(named_port_connection
port_name: (simple_identifier) @variable.member)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(ordered_port_connection
(expression
(primary
(hierarchical_identifier
(simple_identifier) @variable.member))))
(coverage_option
(simple_identifier) @variable.member)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; variable.builtin
(method_call_body
arguments: (list_of_arguments
(expression) @variable.builtin
fix: prefer `#eq?` for checking equality with one string (#8246)
2025-10-29 18:51:42 -07:00
(#eq? @variable.builtin "this")))
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(implicit_class_handle) @variable.builtin
verilog highlight: add some keywords, tidy keywords (#2432) * Add a bunch of the OO keywords and some of the more unusual block delimiter types * Highlight macromodule like module is. * Highlight new as seen in constructor declarations like `class blah; function new(...); ... endfunction endclass` * Make endfunction a @keyword.function. This matches how lua does it. * Make tasks @keyword.function: tasks in SystemVerilog are more or less just impure functions * Highlight casex/casez like case is currently highlighted (previously these were not highlighted at all) * Highlight unique, unique0, priority for constructs like `unique case (...) ... endcase` and `priority if (...) ...`
2022-02-01 23:13:01 -08:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; variable.parameter
(named_parameter_assignment
chore: query formatting
2024-01-06 15:05:50 +09:00
(simple_identifier) @variable.parameter)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(parameter_declaration
(list_of_param_assignments
(param_assignment
(simple_identifier) @variable.parameter)))
(local_parameter_declaration
(list_of_param_assignments
(param_assignment
(simple_identifier) @variable.parameter)))
; function builtin
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
[
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(simulation_control_task)
(system_tf_identifier)
(severity_system_task)
(randomize_call)
(array_or_queue_method_name)
"new"
] @function.builtin
; declaration
(task_body_declaration
.
name: (simple_identifier) @function
(simple_identifier)? @label)
(function_body_declaration
.
name: (simple_identifier) @function
(simple_identifier)? @label)
(function_body_declaration
.
(data_type_or_void)
name: (simple_identifier) @function
(simple_identifier)? @label)
(clocking_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
(sequence_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
(property_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
(class_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
(interface_class_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
(covergroup_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(package_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(checker_declaration
.
name: (simple_identifier) @constructor
(simple_identifier)? @label)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(interface_declaration
.
[
(simple_identifier) @constructor
(interface_nonansi_header
(simple_identifier) @constructor)
(interface_ansi_header
(simple_identifier) @constructor)
]
(simple_identifier)? @label)
(module_declaration
.
[
(simple_identifier) @constructor
(module_nonansi_header
(simple_identifier) @constructor)
(module_ansi_header
(simple_identifier) @constructor)
]
(simple_identifier)? @label)
(program_declaration
.
[
(simple_identifier) @constructor
(program_nonansi_header
(simple_identifier) @constructor)
(program_ansi_header
(simple_identifier) @constructor)
]
(simple_identifier)? @label)
fix(verilog): update queries (#7400) 1. Add "string" as a keyword 2. Fix issue where non-type.builtin fields are captured when using (data_type) as type.builtin 3. Add generate label
2024-11-24 17:44:23 +08:00
(generate_block
name: (simple_identifier) @label)
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; function.call
(method_call_body
name: (simple_identifier) @function.call)
(tf_call
(hierarchical_identifier
(simple_identifier) @function.call))
; instance
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
(module_instantiation
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
instance_type: (simple_identifier) @constructor)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
(name_of_instance
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
instance_name: (simple_identifier) @module)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(sequence_instance
(hierarchical_identifier
(simple_identifier) @module))
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(udp_instantiation
(simple_identifier) @constructor)
(ansi_port_declaration
(interface_port_header
interface_name: (simple_identifier) @variable
modport_name: (simple_identifier) @variable.member)
port_name: (simple_identifier) @variable)
; bind
(bind_directive
(bind_target_scope
(simple_identifier) @constructor))
(bind_target_instance
(hierarchical_identifier
(simple_identifier) @module))
; assertion
(concurrent_assertion_item
(simple_identifier) @label)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; converge
(cover_point
name: (simple_identifier) @label)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(cover_cross
name: (simple_identifier) @module)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(list_of_cross_items
(simple_identifier) @constructor)
;package
(package_import_item
(simple_identifier) @constructor)
; label
(seq_block
(simple_identifier) @label)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(statement
block_name: (simple_identifier) @label)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; dpi
(dpi_spec_string) @string
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
c_name: (c_identifier) @function
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(dpi_import_export
name: (simple_identifier) @function)
Add locals for verilog
2020-11-18 21:38:58 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; type def
(class_type
(simple_identifier) @constructor)
(class_type
(simple_identifier)
chore: query formatting
2024-01-06 15:05:50 +09:00
(simple_identifier) @type)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(data_type
(class_scope
(class_type
(simple_identifier) @constructor)))
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(task_prototype
name: (simple_identifier) @function)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(function_prototype
name: (simple_identifier) @function)
(type_assignment
name: (simple_identifier) @type.definition)
(interface_class_type
(simple_identifier) @type.definition)
(package_scope
(simple_identifier) @constructor)
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(data_declaration
(type_declaration
type_name: (simple_identifier) @type.definition))
Add verilog/systemverilog queries
2020-08-28 18:11:10 +02:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(net_declaration
chore: query formatting
2024-01-06 15:05:50 +09:00
(simple_identifier) @type)
Improve highlighting for generate blocks
2020-11-16 18:32:51 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
(constraint_declaration
(simple_identifier) @constructor)
(method_call
(primary
(hierarchical_identifier
(simple_identifier) @constructor)))
(string_literal
(quoted_string) @string)
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
; include
(include_statement
(file_path_spec) @string.special.path)
; directive
Improve highlighting of port declarations in verilog
2020-11-17 18:16:35 +01:00
[
feat(systemverilog)!: update parser and queries Breaking changes: 1. `(comment)` node split into `(one_line_comment)` and `(block_comment)` 2. named `(directive_foo)` nodes replaced by anonymous `"'foo"` (with backtick!) nodes -- but not consistently
2025-08-01 18:15:49 +02:00
"`define"
"`default_nettype"
(resetall_compiler_directive)
"`timescale"
"`undef"
(undefineall_compiler_directive)
"`ifdef"
"`ifndef"
"`elsif"
"`endif"
"`else"
feat(verilog)!: use systemverilog parser and queries (#7170)
2024-10-16 08:35:35 +02:00
] @keyword.directive.define
(include_compiler_directive
(quoted_string) @string.special.path)
(include_compiler_directive
(system_lib_string) @string)
(default_nettype_compiler_directive
(default_nettype_value) @type.builtin)
(text_macro_definition
(text_macro_name
(simple_identifier) @keyword.directive))
(text_macro_usage) @keyword.directive
(ifdef_condition
(simple_identifier) @keyword.directive)
(undefine_compiler_directive
(simple_identifier) @keyword.directive)
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